The invention deals with a process suitable for manufacturing monolithic integrated highest-frequency circuits which each contain at least one integrated bipolar planar transistor, and also still other integrated components, such as insulated-gate field-effect transistors, integrated capacitors or integrated resistors. The process to be disclosed by this invention as well as the discussion of the state of the art, in order to facilitate the understanding and to simplify the description, however, is referred to as a process for manufacturing a monolithic integrated circuit of the type comprising at least one bipolar planar transistor. Thus, no restriction is to be seen in this, especially since it has long since been known to manufacture a number of monolithic integrated circuits on a larger semiconductor wafer from which the individual circuits are cut and which are only thereafter encapsulated individually.
A process of this kind has already been disclosed previously in the German Offenlegungsschrift DE-A 32 43 059 or DE-A 31 29 5239. In that process used doped polycrystalline silicon layers are used in order in a self-aligning manner to fabricate the base-contacting region with its base electrode and to fabricate the emmiter region with its emitter electrode in a direct or close proximity in relation to each other. In that way it is possible to achieve a very low base lead-in resistance and a relatively high operating speed. Moreover, such a self-aligning process basically offers the advantage that safety distances in the photolithographic processes can be reduced to a minimum, so that the side dimensions of the bipolar planar transistors can likewise be reduced. The disadvantage of the process as disclosed in the aforementioned German Offenlegungsschrift DE-A 31 29 539 is that an expensive epitaxial process is used which, according to experience, only permits a small yield. One disadvantage of the process disclosed in the German Offenlegungsschrift DE-A 32 43 059 as likewise referred to hereinafter, resides in that the overlapping capacity between both the emitter electrode and the base electrode which capacitance restricts the operating speed.
The invention, therefore, starts out from the process as disclosed in the European Patent Application EP-A-71 665 which has substantially overcome the aforementioned disadvantages, by taking up the idea as disclosed in DE-OS (German Offenlegungsschrift) 31 29 539, of providing the lead (series) resistance of the polycrystalline silicon electrodes, which transition into conducting conductor leads, with superficial layers of silicide in order thus to reduce the lead-in resistance. At the same time, this causes an increase of the operating speed of the monolithic integrated circuit.
While the aforementioned German Offenlegungsschriften (DE-OS's) do not deal with the manufacture or fabrication of the collector electrode, it is the case with one type of embodiment of the process as disclosed in the European Patent Application EP-A-71 665, that the collector contacting region is made in a self-aligned manner with regard to both the emitter region and the base contacting region which manner, however, does not apply to the fabrication of the contacts to the regions to be contacted.
In the conventional process as disclosed in the aforementioned European Patent Application EP-A-71 665, for manufacturing a monolithic integrated circuit having at least one bipolar planar transistor, the collector region lies on one main surface of a semiconductor substrate, and is formed on this surface within the opening or window of a layer of field oxide, to wit, a collector area. For manufacturing both the emitter region and the base region in a self-aligned manner in relation to one another, the emitter area is covered with an oxidation masking layer portion of a first oxidation making layer of thickness such that the latter, in the course of an ion implantation process of high energy, is penetrated by dopants of the base region and, in the course of another ion implanation process of low energy, marks the dopants from the base region. Following the implanation processes, which are carried out by using an implanation mask defining the base area, the exposed semiconductor surface is thermally oxidized by forming an oxide frame surrounding the emitter area, whereupon the first oxidation masking layer portion is removed. Finally, the main surface is covered with a layer of foreign oxide in which is defined contact openings (windows) over the regions which are contacted through the openings by electrodes. The contacting of the regions, as is customary with planar integrated circuits, is effected by way of conductor leads extending on thermally produced oxide and/or on a layer of foreign oxide and which, through contact openings (windows) defined in these insulating layers, serve to contact the regions, or else is effected by the electrodes as are already attached to the regions.